1 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f81025c june 2001 rev. 6 eco #14326 the edi8f81025c is an 8mb cmos static ram based on two 512kx8 static rams mounted on a multi-layered epoxy laminate (fr4) substrate. a low power version with data retention (edi8f81025lp) is also available. all inputs and outputs are ttl compatible and operate from a single 5v supply. fully asynchronous, the edi8f81025c requires no clocks or refreshing for operation. features ?1m x 8 bit cmos static ram ? access times 70 through 100ns ? data retention function (edi8f81025lp) ? ttl compatible inputs and outputs ? fully static, no clocks ?high density packaging ? 36 pin dip, no. 180 ?single +5v (10%) supply operation pin configurations and block diagram description 1 m x 8 static ram cmos, module fig. 1 pin names 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 nc a19 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 vss 8f81025c pin config 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 vcc nc nc a15 a17 w a13 a8 a9 a11 g a10 e dq7 dq6 dq5 dq4 dq3 a?-a18 w a19 e dq?-dq7 decoder g 8f81025c blk dia. 512k x 8 512k x 8 a?-a19 address inputs e chip enable w write enable g output enable dq?-dq7 common data input/output vcc power (+5v10%) vss ground nc no connection
2 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f81025c june 2001 rev. 6 eco #14326 absolute maximum ratings* recommended dc operating conditions dc electrical characteristics *typical: ta = 25c, vcc = 5.0v capacitance truth table (f=1.0mhz, vin=vcc or vss) ac test conditions these parameters are sampled, not 100% tested. *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on any pin relative to vss -0.5v to 7.0v operating temperature ta (ambient) commercial 0c to +70c industrial -40c to +85c storage temperature -55c to +125c power dissipation 1 watt output current 20 ma (note: for tehqz, tghqz and twlqz, cl=5pf) parameter sym min typ max units supply voltage vcc 4.5 5.0 5.5 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- 6.0 v input low voltage vil -0.3 -- 0.8 v iinput pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load 1ttl, cl =100pf parameter sym conditions min typ* max units operating power icc1 w, e = vil, ii/o = 0ma, -- 100 140 ma supply current min cycle standby (ttl) power icc2 e > vih, vin < vil -- 25 55 ma supply current vin > vih full standby power icc3 e > vcc-0.2v c -- 1.5 2 ma supply current (cmos) vin > vcc-0.2v or lp -- 200 300 a vin< 0.2v input leakage current ili vin = 0v to vcc -10 -- 10 a output leakage current ilo v i/o = 0v to vcc -10 -- 10 a output high voltage voh ioh =-1.0ma 2.4 -- -- v output low voltage vol iol = 2.1ma -- -- 0.4 v g e w mode output power x h x standby high z icc2, icc3 h l h output deselect high z icc1 l l h read dout icc1 x l l write din icc1 parameter sym max unit address lines ci 30 pf data lines cd/q 43 pf chip enable line cc 10 pf write and output enable lines cw 32 pf
3 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f81025c june 2001 rev. 6 eco #14326 ac characteristics read cycle read cycle 1 - w high, g, e low read cycle 2 - w high symbol 70ns 85ns 100ns parameter jedec alt. min max min max min max units read cycle time t avav trc 70 85 100 ns address access time tavqv taa 70 85 100 ns chip enable access time telqv tacs 70 85 100 ns chip enable to output in low z (1) telqx tclz 5 5 5 ns chip disable to output in high z (1) tehqz tchz 30 35 40 ns output hold from address change tavqx toh 5 5 5 ns output enable to output valid tglqv toe 40 45 50 ns output enable to output in low z (1) tglqx tolz 5 5 5 ns output disable to output in high z(1) tghqz tohz 30 35 40 ns fig. 3 fig. 2 note 1: parameter guaranteed, but not tested address 1 address 2 tavav data 1 data 2 tavqv tavqx 8f81025c rd cyc1 a q tghqz telqv telqx e g q tehqz a tavav tglqv tglqx tavqv 8f81025c rd cyc2
4 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f81025c june 2001 rev. 6 eco #14326 ac characteristics write cycle note 1: parameter guaranteed, but not tested. write cycle 1 - w controlled symbol 70ns 85ns 100ns parameter jedec alt. min max min max min max units write cycle time tavav twc 70 85 100 ns chip enable to end of write telwh tcw 65 70 80 ns teleh tcw 65 70 80 ns address setup time tavwl tas 0 0 0 ns tavel tas 0 0 0 ns address valid to end of write tavwh taw 65 70 80 ns taveh taw 65 70 80 ns write pulse width twlwh twp 65 70 80 ns twleh twp 65 70 80 ns write recovery time twhax twr 5 5 5 ns tehax twr 5 5 5 ns data hold time twhdx tdh 0 0 0 ns tehdx tdh 0 0 0 ns write to output in high z (1) twlqz twhz 0 30 0 35 0 40 ns data to write time tdvwh tdw 30 35 40 ns tdveh tdw 30 35 40 ns output active from end of write (1) twhqx twlz 5 5 5 ns fig. 4 e a tavav telwh tavwh twlwh tavwl twhax w high z data valid twlqz twhqx tdvwh twhdx q d 8f81025c write cyc1
5 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f81025c june 2001 rev. 6 eco #14326 write cycle 2 e controlled data retention characteristics lp version only characteristic sym test conditions vdd min typ max unit 70c 85c data retention voltage vdd 2 -- -- -- v data retention quiescent current iccdr e > vdd -0.2v 2v -- 100 130 a vin > vdd -0.2v 3v -- 160 210 a chip disable to data retention time tcdr(1) or vin < 0.2v 0 -- -- -- ns operation recovery time tr (1) t avav* -- -- -- ns note: parameter guaranteed, but not tested * read cycle time fig. 5 data retention - e controlled fig. 6 a tavel high z tavav 8f81025c write cyc2 teleh e taveh tehax w twleh tehdx tdveh q data valid d vcc tr 8f81025c data retent. data retention mode e tcdr e 3 vdd-0.2v vdd 4.5v 4.5v
6 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f81025c june 2001 rev. 6 eco #14326 ordering information package no. 180: 36 pin dual-in-line package package description 0.670 max. 2.010 max. 0.150 ref. 17 x 0.100 1.700 ref. 0.175 0.125 0.220 max. 0.620 0.590 0.100 typ. 8f81025c pkg note: to order an industrial grade product substitute the letter c in the suffix with the letter i, eg. edi8f81025c70b6c becomes edi8f81025c70b6i. standard power low power speed package with data retention (ns) no. edi8f81025c70b6c edi8f81025lp70b6c 70 180 edi8f81025c85b6c edi8f81025lp85b6c 85 180 edi8f81025c100b6c EDI8F81025LP100B6C 100 180 all dimensions are in inches
|
